 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS The MC54/74HC595A is identical in pinout to the LS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC595A consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 328 FETs or 82 Equivalent Gates * Improvements over HC595 -- Improved Propagation Delays -- 50% Lower Quiescent Power -- Improved Input Noise and Latchup Immunity MC54/74HC595A J SUFFIX CERAMIC PACKAGE CASE 620-10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 16 1 DT SUFFIX TSSOP PACKAGE CASE 948F-01 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP LOGIC DIAGRAM SERIAL DATA INPUT 14 15 PIN ASSIGNMENT QB QC QD PARALLEL DATA OUTPUTS QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA A OUTPUT ENABLE LATCH CLOCK SHIFT CLOCK RESET SQH QA 1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH A SHIFT REGISTER LATCH SHIFT 11 CLOCK 10 RESET LATCH 12 CLOCK OUTPUT 13 ENABLE VCC = PIN 16 GND = PIN 8 9 SQH SERIAL DATA OUTPUT 10/95 (c) Motorola, Inc. 1995 1 REV 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC595A Symbol Vin, Vout Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin PD TL VOH tr, tf Iin VOL TA VIH VIL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Maximum Low-Level Output Voltage, QA - QH Minimum High-Level Output Voltage, QA - QH Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| Vin = VIH or VIL |Iout| |Iout| Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 - 65 to + 150 - 0.5 to + 7.0 2 - 55 Min 2.0 Value v 6.0 mA v 7.8 mA v 6.0 mA v 7.8 mA 0 0 0 0 75 35 20 260 300 750 500 450 + 125 1000 500 400 VCC Max 6.0 VCC V 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C ns V V V V V - 55 to 25_C 0.5 1.35 1.8 1.5 3.15 4.2 0.26 0.26 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 1.35 1.8 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 v 0.5 1.35 1.8 1.5 3.15 4.2 0.4 0.4 0.1 0.1 0.1 3.7 5.2 1.9 4.4 5.9 v Unit V V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 300 pF 2 f + ICC VCC . For load considerations, see Chapter 2 of the * Used to determine the no-load dynamic power consumption: PD = CPD VCC Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) DC ELECTRICAL CHARACTERISTICS (Continued) Symbol Symbol VOH tPLH, tPHL tPLH, tPHL tTLH, tTHL tTLH, tTHL tPZL, tPZH tPLZ, tPHZ VOL tPHL fmax CPD Cin Cout ICC IOZ Iin Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current, QA - QH Maximum Input Leakage Current Maximum Low-Level Output Voltage, SQH Minimum High-Level Output Voltage, SQH Power Dissipation Capacitance (Per Package)* Maximum Three-State Output Capacitance (Output in High-Impedance State), QA - QH Maximum Input Capacitance Maximum Output Transition Time, SQH (Figures 1 and 7) Maximum Output Transition Time, QA - QH (Figures 3 and 7) Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8) Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8) Maximum Propagation Delay, Latch Clock to QA - QH (Figures 3 and 7) Maximum Propagation Delay, Reset to SQH (Figures 2 and 7) Maximum Propagation Delay, Shift Clock to SQH (Figures 1 and 7) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 7) Parameter Parameter Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VIH or VIL IIoutI 20 A Vin = VIH or VIL IIoutI 20 A Vin = VCC or GND lout = 0 A Vin = VCC or GND Vin = VIH or VIL IIoutI 4.0 mA IIoutIv 5.2 mA Vin = VIH or VIL IIoutI 4.0 mA IIoutIv 5.2 mA v v Test Conditions 3 v v VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 6.0 6.0 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 -- -- - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 0.5 0.1 0.26 0.26 3.98 5.48 135 27 23 150 30 26 140 28 24 145 29 25 140 28 24 6.0 30 35 4.0 0.1 0.1 0.1 1.9 4.4 5.9 15 10 75 15 13 60 12 10 Guaranteed Limit Guaranteed Limit v 85_C v 125_C v 85_C v 125_C 5.0 1.0 0.33 0.33 3.84 5.34 170 34 29 190 38 33 175 35 30 180 36 31 175 35 30 4.8 24 28 0.1 0.1 0.1 1.9 4.4 5.9 15 10 95 19 16 75 15 13 40 MC54/74HC595A 1.0 10 205 41 35 225 45 38 210 42 36 220 44 38 210 42 36 160 110 22 19 4.0 20 24 0.4 0.4 0.1 0.1 0.1 3.7 5.2 1.9 4.4 5.9 15 10 90 18 15 MOTOROLA MHz Unit Unit A A A pF pF ns ns ns ns ns ns ns V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I TIMING REQUIREMENTS (Input tr = tf = 6.0 ns) MOTOROLA SR = shift register contents LR = latch register contents MC54/74HC595A Force outputs into high impedance state Enable parallel outputs Latch register remains unchanged Transfer shift register contents to latch register Shift register remains unchanged Shift data into shift register Reset shift register Symbol trec tr, tf tsu tsu tw tw tw th Operation Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, Latch Clock (Figure 6) Minimum Pulse Width, Shift Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) Reset H H H X X X L D = data (L, H) logic level U = remains unchanged Serial Input A D X X X X X X Parameter L, H, L, H, Shift Clock Inputs X X X X FUNCTION TABLE L, H, L, H, L, H, L, H, Latch Clock X X X = don't care Z = high impedance 4 Output Enable H L L L L L L D SRA; SRN SRN+1 Shift Register Contents VCC V U U L * * * 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25_C to - 55_C 1000 500 400 5.0 5.0 5.0 50 10 9.0 50 10 9.0 50 10 9.0 50 10 9.0 60 12 10 75 15 13 Latch Register Contents ** ** U U U U * = depends on Reset and Shift Clock inputs ** = depends on Latch Clock input SRN LRN Resulting Function Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1000 500 400 5.0 5.0 5.0 65 13 11 65 13 11 75 15 13 65 13 11 95 19 16 65 13 11 SRG SRH Serial Output SQH L U U * * * 1000 500 400 110 22 19 5.0 5.0 5.0 75 15 13 75 15 13 90 18 15 75 15 13 75 15 13 Parallel Outputs QA - QH U Enabled SRN U U U Unit ns ns ns ns ns ns ns ns Z MC54/74HC595A PIN DESCRIPTIONS INPUTS A (Pin 14) Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register. CONTROL INPUTS Shift Clock (Pin 11) Shift Register Clock Input. A low- to-high transition on this input causes the data at the Serial Input pin to be shifted into the 8-bit shift register. Reset (Pin 10) Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected. Latch Clock (Pin 12) Storage Latch Clock Input. A low-to-high transition on this input latches the shift register data. Output Enable (Pin 13) Active-low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (QA-QH) into the high- impedance state. The serial output is not affected by this control unit. OUTPUTS QA - QH (Pins 15, 1, 2, 3, 4, 5, 6, 7) Noninverted, 3-state, latch outputs. SQH (Pin 9) Noninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register. This output does not have three-state capability. High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC595A SWITCHING WAVEFORMS tr SHIFT CLOCK 90% 50% 10% tw 1/fmax tPLH OUTPUT SQH 90% 50% 10% tTLH tTHL tPHL tf VCC GND RESET tPHL OUTPUT SQH SHIFT CLOCK 50% trec VCC 50% GND 50% GND tw VCC Figure 1. VCC GND tPLH 90% QA-QH 50% OUTPUTS 10% tTLH tTHL tPHL OUTPUT ENABLE Figure 2. VCC 50% GND tPZL OUTPUT Q 50% tPZH OUTPUT Q 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE LATCH CLOCK 50% Figure 3. SHIFT CLOCK Figure 4. VCC 50% GND tsu LATCH CLOCK 50% GND tw VCC VALID SERIAL INPUT A VCC 50% GND tsu LATCH CLOCK th 50% VCC GND Figure 5. Figure 6. TEST CIRCUITS TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* CL* * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 7. Figure 8. MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC595A EXPANDED LOGIC DIAGRAM OUTPUT ENABLE LATCH CLOCK SERIAL DATA INPUT A 13 12 14 D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D Q D LRA Q 15 QA Q D LRB Q 1 QB Q D LRC Q 2 QC Q D LRD Q 3 QD PARALLEL DATA OUTPUTS Q D LRE Q 4 QE Q D LRF Q 5 QF Q D LRG Q 6 QG SHIFT CLOCK Q SRH D LRH Q 7 QH 11 R 10 RESET 9 SERIAL DATA OUTPUT SQH High-Speed CMOS Logic Data DL129 -- Rev 6 7 MOTOROLA MC54/74HC595A TIMING DIAGRAM SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE QA QB QC QD QE QF QG QH SERIAL DATA OUTPUT SQH NOTE: implies that the output is in a high-impedance state. MOTOROLA 8 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC595A OUTLINE DIMENSIONS -A - 16 9 J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -B - C L 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -T SEATING - PLANE N E F G D 16 PL 0.25 (0.010) M K M J 16 PL 0.25 (0.010) M TB S TA S DIM A B C D E F G J K L M N -A - 16 9 N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M -A - 16 9 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -B - 1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S High-Speed CMOS Logic Data DL129 -- Rev 6 9 MOTOROLA MC54/74HC595A OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 2X L/2 16 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ M DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 10 *MC54/74HC595A/D* EE CC EE CC EE CC EE CC -W- MC54/74HC595A/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
Price & Availability of MC54HC595
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |